1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a TiN barrier layer which is uniformly deposited by chemical-vapor deposition across the exposed surfaces of a trench into which an interconnect is to be formed.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application. It is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization structure has also increased.
Building multi-level interconnect structures is well known in the art. Multi-level interconnect structures were developed in response to the shrinkage of active devices combined with increased demands required to accommodate interconnect routed between the active devices. In many designs, the area required to route a level of interconnect exceeds the area occupied by the active devices. Multi-level interconnect technology has therefore gained in popularity. Interconnect dispersed across several elevational levels helps reduce the overall lateral area occupied by the interconnect--leading to an increase in integrated circuit packing density.
Local interconnects are a special form of interconnect. Local interconnects are relatively short routing structures, and can be made of numerous conductive elements. A popular local interconnect comprises doped polysilicon, or reacted polysilicon termed "polycide". In whatever form, local interconnects are beneficial to the formation of multi-level interconnect structures. Contact of a local interconnect to the underlying silicon substrate is typically made by forming a trench through an interposed dielectric down to the underlying substrate. A conductive material may be deposited into the trench to form a local interconnect across the substrate which is isolated everywhere else. Local interconnects, when covered with a dielectric, permit "global" interconnect to extend in an unrestricted manner a dielectric-spaced distance over the local interconnects and buried contacts. Local interconnects are not as universal as global interconnects for various reasons. First, a local interconnect cannot cross over regions where a transistor gate exists without making a contact to the gate. Second, local interconnects are typically composed of a material which has a resistivity higher than that from which global interconnects (e.g., aluminum) are formed.
Local interconnect can be used to provide coupling between a gate of a MOS transistor and a source or drain active area (hereinafter "junction") of that transistor. Such coupling effectuates a diode. Local interconnect has also been used to couple a gate of one transistor and a source or drain junction of another transistor. This form of coupling is prevalent in, for example, high density VLSI logic and SRAMs. An SRAM cell layout can be substantially reduced when a local interconnect level and associated buried contacts are used.
FIG. 1 illustrates an exemplary SRAM cell 10 which includes a pair of cross-coupled transistors 12 and a pair of access transistors 14. The drain junction of each transistor 14 is coupled to the gate of one of the transistors 12 via a local interconnect. Application of a word bit (W0 and W1) will force the output from transistors 12 to undergo a change in state when a sufficient voltage magnitude and duration of bit input (B0 or B1) exists. SRAM cells include several devices (four are shown) which somewhat limit the packing density of these cells. However, as SRAMs have evolved, they have undergone an increase in density mostly due to the use of smaller line widths. Density improvements have also been made by using, for example, local interconnects, and poly load resistors in lieu of devices. SRAM cell 10 has four devices and two poly load resistors 16. In such a four-transistor cell having two poly load resistors, there are no P-channel devices, so no N-channel-to-P-channel isolation is needed. Advantageously, the local interconnects function as gate-to-drain interconnect structures.
FIG. 2 depicts a partial top plan view of an exemplary integrated circuit employing such a local interconnect. A pair of transistors 20 and 22 are arranged a lateral spaced distance apart upon and within a substrate. Transistors 20 and 22 comprise respective gate conductors 24 and 26 interposed between respective source/drain junctions 28 and 30. Those source/drain junctions 28 and 30 are isolated from each other by field regions (e.g., shallow trench isolation structures) formed within the substrate. A local interconnect 32 extends across the substrate from gate conductor 24 of transistor 20 to one source/drain junction 30 of transistor 22. The local interconnect 32 is oriented such that it does not pass over source/drain junctions 28 and cause unwanted shorting between gate conductor 24 and source/drain junctions 28.
FIG. 3a illustrates a cross-sectional view along plane A--A of the integrated circuit depicted in FIG. 2. Source/drain junction 30 is arranged within a semiconductor substrate 34 comprising single crystalline silicon. Source/drain junction 30 has been implanted with a dopant species opposite in type to the dopant species residing within the bulk of substrate 34. A silicide structure may be formed upon source/drain junction 30 to lower the contact resistance to the junction. Trench isolation structures 36 comprising, e.g., silicon dioxide ("oxide") are arranged on opposite sides of source/drain junction 30 within substrate 34. The upper surface of each trench isolation structure 36 includes a recessed region directly adjacent source/drain junction 30, and thereby exposes a lateral edge of the junction. The formation of such a recessed region in the upper surface of a trench isolation structure is well-known in the semiconductor industry. It is believed that the recessed region results from overetching layers of material patterned upon the substrate, thereby removing the field oxide underlying those layers of material. As shown in FIG. 3a, a titanium (Ti) layer 40 and a titanium nitride (TiN) layer 42 are arranged at the periphery of local interconnect 44. Local interconnect 44 is laterally isolated from other conductive structures of the integrated circuit by an interlevel dielectric 38.
Turning to FIG. 3b, a detailed view along section 46 of FIG. 3a is shown in which the topological surface includes a recessed region. The lateral edge of source/drain region 30, not being covered with trench isolation structure 36, is partially coated with Ti layer 40 and TiN layer 42. Sputter etch may be used to clean the exposed silicon/silicide and oxide surfaces prior to receiving Ti layer 40. Conventional methods of local interconnect formation involve physical vapor deposition ("PVD") of Ti and TiN onto exposed surfaces, followed by deposition of a conductive material, such as tungsten (W) upon the TiN. PVD of Ti and TiN may be accomplished by, e.g., reactive sputtering a titanium target in an inert ambient such as argon or N.sub.2. Ti layer 40 and TiN layer 42 together serve as a diffusion barrier to cross-diffusion at the interconnect 44/junction 30 interface. TIN is a popular diffusion barrier because it exhibits good electrical conductivity, chemical inertness, and strong atomic bonds. Such cross-diffusion, if not prevented, could lead to problems such as the formation of a conductive path through junction 30, i.e., "junction spiking", which provides undue leakage or renders transistor 22 inoperable. Ti layer 40 combined with TiN layer 42 also provide an adhesion/nucleation layer between the tungsten within interconnect 44 and the sidewalls of interlevel dielectric 38.
Unfortunately, several problems are associated with lining the recessed region of the semiconductor topography with Ti layer 40 and TiN layer 42 which are formed by conventional PVD. Since PVD is a line-of-sight process in which deposition is directional and occurs on the first encountered surface, the step coverage of TiN layer 42 is dependent on the orientation of the topological features to the dielectrically induced deposition material. Dependency on the orientation is often referred to as a "collimated" deposition in that columns of deposited material accumulate generally perpendicular to horizontally oriented topological surfaces. Unfortunately, vertical surfaces, due to their orientation, cannot receive collimated deposition materials. Thus, the lateral sidewall of source/drain junction 30 receive minimal and non-continuous PVD Ti and TiN. The Ti and TiN that enters the narrow recess region strikes the upper portions of the vertically oriented surfaces of source/drain junction 30 and the recessed region of trench isolation structure 36 before reaching the lower portions of those surfaces.
As shown, lower portions of the lateral sidewall of source/drain junction 30 and of the recessed region of isolation structure 36 may receive very little Ti and TiN, and thus remain exposed after the PVD of Ti layer 40 and TiN layer 42. As such, during the chemical-vapor deposition ("CVD") of W fill material 44 (i.e., local interconnect 44) from a gas comprising SiH.sub.4 and WF.sub.6 or WF.sub.4, a F radical attacks the exposed Si and SiO.sub.2 surfaces not sufficiently coated with Ti layer 40 and TiN layer 42, most likely forming a SiF layer. The amount of WF.sub.6 available to react with SiH.sub.4 to form W is thus significantly reduced at those surfaces covered by SiF layer. At the surfaces lined with Ti layer 40 and TiN layer 42, however, cross-diffusion between the silicon atoms and the fluorine atoms is reduced, making SiF formation less likely. Absent, an adequate diffusion barrier at those lower portions of the lateral sidewall of source/drain junction 30 and the recess region of isolation structure 36, W atoms might undesirably migrate into source/drain junction 30 and isolation structure 36 in subsequent processing steps.
In addition, TiN layer 42 may inadequately cover the lower portions of Ti layer 40. Thus, as W is PVD deposited into the recessed region, a F radical arising from either WF.sub.6 or WF.sub.4 may attack the exposed portions of Ti layer 40, thereby forming TiF. Unfortunately, TiF exhibits a relatively high resistivity which is greater than that of the combination of Ti layer 40 and TiN layer 42. Thus, the formation of TiF may unduly add to the contact resistance between junction 30 and W fill material 44. Furthermore, if TiSi.sub.2 exists upon source/drain junction 30, WF.sub.6 might penetrate to and react with the TiSi.sub.2. Consequently, non-continuous regions of TiF mighty be created in the salicide (i.e., TiSi.sub.2) structure, leading to highly resistive transistors and contact structures.
Another problem related to using PVD to form Ti layer 40 and TiN layer 42 is that these layers may become delaminated from the surfaces upon which they are formed if they are too thin or if TiF and/or SiF are formed. Collimation of Ti layer 40 and TiN layer 42 provides diffusion pathways at the grain boundaries between each "column" of the structure. As a result, silicon in the adjacent junction 30 may migrate into W fill material 44, leaving behind voids or pits into which W may diffuse. In addition, the PVD Ti and TiN columnar microstructure grains may form diffusion pathways through the thin barrier layer to further aggravate the TiF and SiF problem. Consequently, the W may accumulate such that it extends through junction 30 to bulk substrate 34, resulting in junction spiking or leakage.
It would therefore be desirable to develop a technique for forming a local interconnect which is lined with a substantially conformal barrier layer. A barrier layer which exhibits good step coverage on the sidewalls and base of a narrow recessed region is necessary to prevent cross-diffusion of atoms between the local interconnect and e.g., an adjacent junction. Further, lining the local interconnect with a barrier layer of uniform thickness will prevent the formation of voids in the ensuing conductive fill material of the local interconnect. Good adhesion between the fill material and the barrier layer is also necessary. Yet further, it would beneficial to form a barrier layer which is not collimated at the perimeter of a local interconnect. Instead, the barrier layer should have a somewhat amorphous grain structure. Undesirable occurrences, such as junction spiking/leakage and increased contact resolution would be less likely in an integrated circuit employing a local interconnect having such a barrier layer at its periphery.